The present inventive concept herein relates a semiconductor memory device, and more particularly, to a semiconductor memory device for a mobile electronic devices.
Semiconductor memory devices such as a low-power double data rate (LPDDR) synchronous dynamic random access memories (SDRAMs) may be used in mobile electronic devices such as smartphones, tablet PCs, ultra-books, and the like.
As program size of mobile operating systems (OS) becomes greater to support multi-tasking, mobile DRAMs are required to consume less power and to operate at higher speed.
In the case where a mobile electronic device is equipped with an application processor (AP) with multiple cores, a low power semiconductor memory device such as LPDDR SDRAM may be utilized as a working memory of the AP.
Semiconductor memory devices for mobile electronic devices use a DQS clocking method in which a data output strobe signal is received from the AP during a write operation, and an internally generated data output strobe signal is sent to the AP during a read operation. A system clock may be provided from the AP in write and read modes of operation. The DQS clocking method needs a margin tDQSS between data and the data output strobe signal. As operating frequency of semiconductor memory devices becomes higher, the margin tDQSS between data and the data output strobe signal becomes tighter and may cause a failure of write operation.
The clocking method may be changed so that a semiconductor memory device receives a system clock and a data clock from the AP in write and read operations, instead of a data output strobe signal as described above. For clear and concise description, such clocking operating method is referred to as a “WCLK clocking operating method”. For the WCLK clocking operating method, the data clock remains at a free running state until the semiconductor memory device transitions to a power-down mode.